A Comparison of Space Grade FPGAs Part 1

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A Comparison of Space Grade FPGAs Part 1
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   A comparison of space-grade FPGAs, Part 1 Rajan Bedi  - June 09, 2014Space-grade FPGAs are offered in three major process technologies: SRAM, flash and antifuse. SRAM-based FPGAs  are volatile and need to be re-programmed at each power-up. This easesprototyping and allows devices to be completely re-configured in-orbit. SRAM configuration memorycan be sensitive to radiation effects which can potentially corrupt a design and alter the intendedoperation. Some space-grade devices use the standard, un-hardened, six-transistor, storage cell inthe functional logic blocks, while more SEU-robust parts exploit the radiation tolerance advantagesof a 12-transistor design at the expense of increased area and power consumption. Continued CMOSscaling has helped to alleviate these disadvantages somewhat.  Flash-based FPGAs  are non-volatile, live at power-up, and can be re-programmed in-orbit. A floating-gate transistor is used within each cell which is immune to firm errors as exposure to radiationcannot generate sufficient charge to change its configuration state. Flash memory cells typicallyrequire two transistors resulting in increased logic density, shorter routing, smaller interconnectdelays and lower power consumption compared to SRAM devices.  Antifuse-based FPGAs  are non-volatile, live at power-up, but one-time programmable, which canpresent prototyping challenges. The antifuses which configure the interconnect are grown betweenthe upper two layers of metal eliminating the routing channels and switching resources betweenlogic modules. This results in increased logic density, shorter routing and smaller delays. AntifuseFPGAs also consume less static and dynamic power than equivalent SRAM devices.Flash and antifuse FPGAs require additional processing steps compared to bulk CMOS, which hasresulted in the specifications of these devices lagging SRAM-based parts by several generations. Theincreased capacity, the diversity of the resources, faster operation and lower dynamic power offeredby deep-submicron, SRAM-based devices can offset the intrinsic energy consumption and logicdensity advantages of flash and antifuse parts.Smaller geometries have resulted in less dynamic power consumption because of lower core voltages and smaller gate capacitances. However, ultra deep-submicron processes dissipate morestatic energy because of increased leakage and subthreshold currents.CMOS scaling has improved the total-dose and latch-up sensitivity of space-grade microelectronics.Thinner gate oxides trap less positive charge while lower supply voltages and the reduced gain of the parasitic, bipolar, silicon-controlled rectifier bolster total-dose and latch-up immunityrespectively. SEE mitigation has become more challenging as increased logic densities require lessoverall charge to disrupt sensitive locations.Some space-grade FPGAs have been hardened-by-process, fabricated using a CMOS silicon-o--insulator process, or use an epitaxial layer to protect against radiation-induced latch-up.  Other space-grade FPGAs contain intrinsic architectural and circuit-level features to protect againstupsets and transients. One supplier of SRAM-based devices has replaced the standard, six-transistor,functional element with a radiation-hardened, 12-transistor design shown below. Figure 1: Standard and radiation-hardened SRAM storage cells. In the conventional cell, a particle striking node Q may cause the latch to change state resulting inan SEE. In the hardened version, Q is represented at two different nodes and a strike at eithercannot cause an upset. The number of transistors per latch has doubled, which can significantlyreduce the available gate count in a given circuit area.The flip-flops within antifuse FPGAs are typically triplicated and upsets due to single ion strikes are voted out by the unaffected latches.Block RAM and configuration memory contain error detection and correction to protect againstSEUs. To reduce the effects of multi-bit errors, some vendors have interleaved the layout of configuration memory such that physically adjacent errors are separated in the memory map. Thismakes errors appear as separate single-bit upsets enabling them to be repaired.Not all configuration memory is critical to FPGA operation and one supplier allows users to definehierarchical regions in the design and partition this into essential and non-essential bits. Soft-errordetection and correction focuses on those bits necessary for logic design and techniques such asscrubbing and partial configuration can be used to prevent the accumulation of configuration errorsdue to SEEs.Some suppliers provide proprietary tools that automatically triplicate registers, combinational logic, voters, global buffers and I/O to protect against SEUs and SETs. State machines can be protectedagainst SEEs by choosing fault-tolerant coding schemes and third-party EDA vendors also providesoftware which adds triple-mode redundancy to the HDL or during synthesis,  e.g.,  Mentor Graphics'Precision.It's important to note that FPGA SEE mitigation techniques do not prevent upsets nor transients, butallow designs to get through periods of error detection and correction without interruption, therebyreducing the effective FIT rate and increasing design availability.  Initial FPGA comparison The following table lists the devices that were compared for this blog article: Table 1: Candidate space-grade FPGAs For obvious reasons and to maintain my independence, I will not reveal the identity of the FPGAscompared in this article. Most of the devices comprise LUT-based, logic elements, with severalhaving MUX-based, configurable fabric. Other FPGAs have flown or are scheduled to be launched,but this comparison has been restricted to devices that are or will formally become space-qualified.This initial blog post compares the predicted, average, power consumption following synthesis andplace & route, due to the combined effects of different process technologies, diverse fabric types,FPGA size, logic density, the impact of CMOS scaling and hardening.I coded VHDL of a maximal-length, 20-stage, many-to-one LFSR: for each FPGA, this design wassynthesised to map the RTL to the target primitives, followed by placement, routing and post-layoutfunctional verification. Conceptually, the gate-level netlist comprises 20 registers, one two-inputXOR gate and 21 primary I/O.For this initial comparison, I deliberately did not specify any stringent constraints for logic synthesisnor did I improve the floorplan of the routed design. Shift-register macros or proprietary IP coreswere not considered either! Future blog posts in this series will discuss how the performance of thisdesign, as well as more representative, on-board, processing functions can be optimised forimplementation on space-grade, FPGA fabrics. A clock frequency of 50 MHz was used and a maximum toggle rate was assumed for the maximal-length LFSR. The ultra-deep-submicron devices can operate at much higher frequency but theslowest FPGA considered in this comparison is limited to 50 MHz. Table 1 lists the predicted,average, power dissipation for all parts: for many of the devices, the energy consumed by the core toimplement this simple LFSR was negligible, dominated mostly by I/O as well as some static leakage.  FPGA vendors offer different tools to predict power consumption: some provide spreadsheets thatestimate dissipation during the project concept phase based on an initial assessment of the logicresources required, I/O loading and activity rates. This information can be entered manually orextracted from the gate-level netlist output by the synthesis tool. The estimate for FPGA #9 wasobtained from a pre-synthesis spreadsheet.Several suppliers offer more accurate predictions following place and route using design-activityinformation generated during simulation (VCD/IEEE 1364 file). Analyses software is available thatreports junction temperature as well as average and cycle-accurate, peak static and dynamic powerconsumption at gate, net, cell, I/O, clock domain and resource level. This more detailed breakdownhas proved to be invaluable on projects!It's important to note that the ultra-deep-submicron, SRAM-based FPGAs listed above contain manyhundreds of thousands of configurable logic elements. At these geometries, static power has muchmore impact on overall consumption and power-driven synthesis is used to lower dissipation. The variation in the predicted energy and the division between dynamic and static consumption due tothe combined effects of different process technologies, diverse fabric types, FPGA size, logic density,the impact of CMOS scaling and hardening is very insightful.
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